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Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt
arm64: ZynqMP DT changes for 6.15 - Align clock nodes with DT binding - Add the first VN-X Versal NET board - Move constants out of DT bindings * tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx: dt-bindings: xilinx: Deprecate header with firmware constants arm64: zynqmp: Use DT header for firmware constants arm64: versal-net: Add description for b2197-00 revA board dt-bindings: soc: Add new VN-X board description based on Versal NET arm64: zynqmp: add clock-output-names property in clock nodes Link: https://lore.kernel.org/r/CAHTX3d+u1VmxP4vm0peQS-ST7o0BuCpKUPRVCSLMfAAb=eV3Xg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2 parents 877fb9a + f0ceedd commit 32e0c5f

14 files changed

Lines changed: 1262 additions & 23 deletions

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‎Documentation/devicetree/bindings/ata/ceva,ahci-1v84.yaml‎

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -163,19 +163,17 @@ additionalProperties: false
163163

164164
examples:
165165
- |
166-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
167166
#include <dt-bindings/interrupt-controller/irq.h>
168167
#include <dt-bindings/power/xlnx-zynqmp-power.h>
169168
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
170-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
171169
#include <dt-bindings/phy/phy.h>
172170
173171
sata: ahci@fd0c0000 {
174172
compatible = "ceva,ahci-1v84";
175173
reg = <0xfd0c0000 0x200>;
176174
interrupt-parent = <&gic>;
177175
interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
178-
clocks = <&zynqmp_clk SATA_REF>;
176+
clocks = <&zynqmp_clk 22>;
179177
ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
180178
ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
181179
ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;

‎Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,6 @@ additionalProperties: false
7575

7676
examples:
7777
- |
78-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
7978
8079
fpd_dma_chan1: dma-controller@fd500000 {
8180
compatible = "xlnx,zynqmp-dma-1.0";
@@ -84,7 +83,7 @@ examples:
8483
interrupts = <0 117 0x4>;
8584
#dma-cells = <1>;
8685
clock-names = "clk_main", "clk_apb";
87-
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
86+
clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>;
8887
xlnx,bus-width = <128>;
8988
dma-coherent;
9089
};

‎Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -193,7 +193,6 @@ additionalProperties: false
193193

194194
examples:
195195
- |
196-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
197196
198197
bus {
199198
#address-cells = <2>;
@@ -204,7 +203,7 @@ examples:
204203
interrupt-parent = <&gic>;
205204
interrupts = <0 56 4>;
206205
reg = <0x0 0xffa50000 0x0 0x800>;
207-
clocks = <&zynqmp_clk AMS_REF>;
206+
clocks = <&zynqmp_clk 70>;
208207
#address-cells = <1>;
209208
#size-cells = <1>;
210209
#io-channel-cells = <1>;

‎Documentation/devicetree/bindings/net/cdns,macb.yaml‎

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -197,7 +197,6 @@ examples:
197197
};
198198
199199
- |
200-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
201200
#include <dt-bindings/power/xlnx-zynqmp-power.h>
202201
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
203202
#include <dt-bindings/phy/phy.h>
@@ -210,9 +209,9 @@ examples:
210209
interrupt-parent = <&gic>;
211210
interrupts = <0 59 4>, <0 59 4>;
212211
reg = <0x0 0xff0c0000 0x0 0x1000>;
213-
clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
214-
<&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
215-
<&zynqmp_clk GEM_TSU>;
212+
clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>,
213+
<&zynqmp_clk 51>, <&zynqmp_clk 50>,
214+
<&zynqmp_clk 44>;
216215
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
217216
#address-cells = <1>;
218217
#size-cells = <0>;

‎Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms
99
maintainers:
1010
- Michal Simek <michal.simek@amd.com>
1111

12-
description: |
13-
Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
12+
description:
13+
AMD/Xilinx boards with ARM 32/64bits cores
1414

1515
properties:
1616
$nodename:
@@ -187,6 +187,13 @@ properties:
187187
- const: qemu,mbv
188188
- const: amd,mbv
189189

190+
- description: Xilinx Versal NET VN-X revA platform
191+
items:
192+
enum:
193+
- xlnx,versal-net-vnx-revA
194+
- xlnx,versal-net-vnx
195+
- xlnx,versal-net
196+
190197
additionalProperties: true
191198

192199
...

‎Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -65,14 +65,13 @@ allOf:
6565

6666
examples:
6767
- |
68-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
6968
soc {
7069
#address-cells = <2>;
7170
#size-cells = <2>;
7271
7372
qspi: spi@ff0f0000 {
7473
compatible = "xlnx,zynqmp-qspi-1.0";
75-
clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
74+
clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>;
7675
clock-names = "ref_clk", "pclk";
7776
interrupts = <0 15 4>;
7877
interrupt-parent = <&gic>;

‎Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml‎

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Original file line numberDiff line numberDiff line change
@@ -101,7 +101,6 @@ examples:
101101
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
102102
#include <dt-bindings/power/xlnx-zynqmp-power.h>
103103
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
104-
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
105104
#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
106105
#include <dt-bindings/phy/phy.h>
107106
axi {
@@ -113,7 +112,7 @@ examples:
113112
#size-cells = <0x2>;
114113
compatible = "xlnx,zynqmp-dwc3";
115114
reg = <0x0 0xff9d0000 0x0 0x100>;
116-
clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
115+
clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
117116
clock-names = "bus_clk", "ref_clk";
118117
power-domains = <&zynqmp_firmware PD_USB_0>;
119118
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,

‎arch/arm64/boot/dts/xilinx/Makefile‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -29,3 +29,5 @@ zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-
2929
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb
3030
zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
3131
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb
32+
33+
dtb-$(CONFIG_ARCH_ZYNQMP) += versal-net-vn-x-b2197-01-revA.dtb

‎arch/arm64/boot/dts/xilinx/versal-net-clk.dtsi‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,231 @@
1+
// SPDX-License-Identifier: GPL-2.0
2+
/*
3+
* dts file for Xilinx Versal NET fixed clock
4+
*
5+
* (C) Copyright 2022, Xilinx, Inc.
6+
* (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc.
7+
*
8+
* Michal Simek <michal.simek@amd.com>
9+
*/
10+
11+
/ {
12+
clk60: clk60 {
13+
compatible = "fixed-clock";
14+
#clock-cells = <0>;
15+
clock-frequency = <60000000>;
16+
};
17+
18+
clk100: clk100 {
19+
compatible = "fixed-clock";
20+
#clock-cells = <0>;
21+
clock-frequency = <100000000>;
22+
};
23+
24+
clk125: clk125 {
25+
compatible = "fixed-clock";
26+
#clock-cells = <0>;
27+
clock-frequency = <125000000>;
28+
};
29+
30+
clk150: clk150 {
31+
compatible = "fixed-clock";
32+
#clock-cells = <0>;
33+
clock-frequency = <150000000>;
34+
};
35+
36+
clk160: clk160 {
37+
compatible = "fixed-clock";
38+
#clock-cells = <0>;
39+
clock-frequency = <160000000>;
40+
};
41+
42+
clk200: clk200 {
43+
compatible = "fixed-clock";
44+
#clock-cells = <0>;
45+
clock-frequency = <200000000>;
46+
};
47+
48+
clk250: clk250 {
49+
compatible = "fixed-clock";
50+
#clock-cells = <0>;
51+
clock-frequency = <250000000>;
52+
};
53+
54+
clk300: clk300 {
55+
compatible = "fixed-clock";
56+
#clock-cells = <0>;
57+
clock-frequency = <300000000>;
58+
};
59+
60+
clk450: clk450 {
61+
compatible = "fixed-clock";
62+
#clock-cells = <0>;
63+
clock-frequency = <450000000>;
64+
};
65+
66+
clk1200: clk1200 {
67+
compatible = "fixed-clock";
68+
#clock-cells = <0>;
69+
clock-frequency = <1200000000>;
70+
};
71+
72+
firmware {
73+
versal_net_firmware: versal-net-firmware {
74+
compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware";
75+
bootph-all;
76+
method = "smc";
77+
};
78+
};
79+
};
80+
81+
&adma0 {
82+
clocks = <&clk450>, <&clk450>;
83+
};
84+
85+
&adma1 {
86+
clocks = <&clk450>, <&clk450>;
87+
};
88+
89+
&adma2 {
90+
clocks = <&clk450>, <&clk450>;
91+
};
92+
93+
&adma3 {
94+
clocks = <&clk450>, <&clk450>;
95+
};
96+
97+
&adma4 {
98+
clocks = <&clk450>, <&clk450>;
99+
};
100+
101+
&adma5 {
102+
clocks = <&clk450>, <&clk450>;
103+
};
104+
105+
&adma6 {
106+
clocks = <&clk450>, <&clk450>;
107+
};
108+
109+
&adma7 {
110+
clocks = <&clk450>, <&clk450>;
111+
};
112+
113+
&can0 {
114+
clocks = <&clk160>, <&clk160>;
115+
};
116+
117+
&can1 {
118+
clocks = <&clk160>, <&clk160>;
119+
};
120+
121+
&gem0 {
122+
clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
123+
};
124+
125+
&gem1 {
126+
clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>;
127+
};
128+
129+
&gpio0 {
130+
clocks = <&clk100>;
131+
};
132+
133+
&gpio1 {
134+
clocks = <&clk100>;
135+
};
136+
137+
&i2c0 {
138+
clocks = <&clk100>;
139+
};
140+
141+
&i2c1 {
142+
clocks = <&clk100>;
143+
};
144+
145+
&i3c0 {
146+
clocks = <&clk100>;
147+
};
148+
149+
&i3c1 {
150+
clocks = <&clk100>;
151+
};
152+
153+
&ospi {
154+
clocks = <&clk200>;
155+
};
156+
157+
&qspi {
158+
clocks = <&clk300>, <&clk300>;
159+
};
160+
161+
&rtc {
162+
/* Nothing */
163+
};
164+
165+
&sdhci0 {
166+
clocks = <&clk200>, <&clk200>, <&clk1200>;
167+
};
168+
169+
&sdhci1 {
170+
clocks = <&clk200>, <&clk200>, <&clk1200>;
171+
};
172+
173+
&serial0 {
174+
clocks = <&clk100>, <&clk100>;
175+
};
176+
177+
&serial1 {
178+
clocks = <&clk100>, <&clk100>;
179+
};
180+
181+
&spi0 {
182+
clocks = <&clk200>, <&clk200>;
183+
};
184+
185+
&spi1 {
186+
clocks = <&clk200>, <&clk200>;
187+
};
188+
189+
&ttc0 {
190+
clocks = <&clk150>;
191+
};
192+
193+
&usb0 {
194+
clocks = <&clk60>, <&clk60>;
195+
};
196+
197+
&dwc3_0 {
198+
clocks = <&clk60>;
199+
};
200+
201+
&usb1 {
202+
clocks = <&clk60>, <&clk60>;
203+
};
204+
205+
&dwc3_1 {
206+
clocks = <&clk60>;
207+
};
208+
209+
&wwdt0 {
210+
clocks = <&clk150>;
211+
};
212+
213+
&wwdt1 {
214+
clocks = <&clk150>;
215+
};
216+
217+
&wwdt2 {
218+
clocks = <&clk150>;
219+
};
220+
221+
&wwdt3 {
222+
clocks = <&clk150>;
223+
};
224+
225+
&lpd_wwdt0 {
226+
clocks = <&clk150>;
227+
};
228+
229+
&lpd_wwdt1 {
230+
clocks = <&clk150>;
231+
};

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