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konradybciorobclark
konradybcio
authored and
robclark
committed
drm/msm/a6xx: Store primFifoThreshold in struct a6xx_info
The if-else monster is so unmaintainable that one case is repeated twice. Get rid of it. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/611092/ [add missing entry to a615 catalog to resolve conflict] Signed-off-by: Rob Clark <robdclark@chromium.org>
1 parent 1b3975e commit 2bbb5fe

3 files changed

Lines changed: 21 additions & 19 deletions

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‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -636,6 +636,7 @@ static const struct adreno_info a6xx_gpus[] = {
636636
.a6xx = &(const struct a6xx_info) {
637637
.hwcg = a612_hwcg,
638638
.protect = &a630_protect,
639+
.prim_fifo_threshold = 0x00080000,
639640
},
640641
/*
641642
* There are (at least) three SoCs implementing A610: SM6125
@@ -666,6 +667,7 @@ static const struct adreno_info a6xx_gpus[] = {
666667
.a6xx = &(const struct a6xx_info) {
667668
.hwcg = a615_hwcg,
668669
.protect = &a630_protect,
670+
.prim_fifo_threshold = 0x0018000,
669671
},
670672
.speedbins = ADRENO_SPEEDBINS(
671673
/*
@@ -694,6 +696,7 @@ static const struct adreno_info a6xx_gpus[] = {
694696
.a6xx = &(const struct a6xx_info) {
695697
.hwcg = a615_hwcg,
696698
.protect = &a630_protect,
699+
.prim_fifo_threshold = 0x00180000,
697700
},
698701
.speedbins = ADRENO_SPEEDBINS(
699702
{ 0, 0 },
@@ -716,6 +719,7 @@ static const struct adreno_info a6xx_gpus[] = {
716719
.init = a6xx_gpu_init,
717720
.a6xx = &(const struct a6xx_info) {
718721
.protect = &a630_protect,
722+
.prim_fifo_threshold = 0x00180000,
719723
},
720724
.speedbins = ADRENO_SPEEDBINS(
721725
{ 0, 0 },
@@ -738,6 +742,7 @@ static const struct adreno_info a6xx_gpus[] = {
738742
.a6xx = &(const struct a6xx_info) {
739743
.hwcg = a615_hwcg,
740744
.protect = &a630_protect,
745+
.prim_fifo_threshold = 0x00018000,
741746
},
742747
.speedbins = ADRENO_SPEEDBINS(
743748
{ 0, 0 },
@@ -760,6 +765,7 @@ static const struct adreno_info a6xx_gpus[] = {
760765
.a6xx = &(const struct a6xx_info) {
761766
.hwcg = a615_hwcg,
762767
.protect = &a630_protect,
768+
.prim_fifo_threshold = 0x00018000,
763769
},
764770
.speedbins = ADRENO_SPEEDBINS(
765771
{ 0, 0 },
@@ -782,6 +788,7 @@ static const struct adreno_info a6xx_gpus[] = {
782788
.a6xx = &(const struct a6xx_info) {
783789
.hwcg = a615_hwcg,
784790
.protect = &a630_protect,
791+
.prim_fifo_threshold = 0x00018000,
785792
},
786793
.speedbins = ADRENO_SPEEDBINS(
787794
{ 0, 0 },
@@ -809,6 +816,7 @@ static const struct adreno_info a6xx_gpus[] = {
809816
.a6xx = &(const struct a6xx_info) {
810817
.hwcg = a630_hwcg,
811818
.protect = &a630_protect,
819+
.prim_fifo_threshold = 0x00180000,
812820
},
813821
}, {
814822
.chip_ids = ADRENO_CHIP_IDS(0x06040001),
@@ -826,6 +834,7 @@ static const struct adreno_info a6xx_gpus[] = {
826834
.a6xx = &(const struct a6xx_info) {
827835
.hwcg = a640_hwcg,
828836
.protect = &a630_protect,
837+
.prim_fifo_threshold = 0x00180000,
829838
},
830839
.speedbins = ADRENO_SPEEDBINS(
831840
{ 0, 0 },
@@ -848,6 +857,7 @@ static const struct adreno_info a6xx_gpus[] = {
848857
.a6xx = &(const struct a6xx_info) {
849858
.hwcg = a650_hwcg,
850859
.protect = &a650_protect,
860+
.prim_fifo_threshold = 0x00300200,
851861
},
852862
.address_space_size = SZ_16G,
853863
.speedbins = ADRENO_SPEEDBINS(
@@ -873,6 +883,7 @@ static const struct adreno_info a6xx_gpus[] = {
873883
.a6xx = &(const struct a6xx_info) {
874884
.hwcg = a660_hwcg,
875885
.protect = &a660_protect,
886+
.prim_fifo_threshold = 0x00300200,
876887
},
877888
.address_space_size = SZ_16G,
878889
}, {
@@ -891,6 +902,7 @@ static const struct adreno_info a6xx_gpus[] = {
891902
.a6xx = &(const struct a6xx_info) {
892903
.hwcg = a660_hwcg,
893904
.protect = &a660_protect,
905+
.prim_fifo_threshold = 0x00200200,
894906
},
895907
.address_space_size = SZ_16G,
896908
.speedbins = ADRENO_SPEEDBINS(
@@ -916,6 +928,7 @@ static const struct adreno_info a6xx_gpus[] = {
916928
.a6xx = &(const struct a6xx_info) {
917929
.hwcg = a640_hwcg,
918930
.protect = &a630_protect,
931+
.prim_fifo_threshold = 0x00200200,
919932
},
920933
}, {
921934
.chip_ids = ADRENO_CHIP_IDS(0x06090000),
@@ -933,6 +946,7 @@ static const struct adreno_info a6xx_gpus[] = {
933946
.a6xx = &(const struct a6xx_info) {
934947
.hwcg = a690_hwcg,
935948
.protect = &a690_protect,
949+
.prim_fifo_threshold = 0x00800200,
936950
},
937951
.address_space_size = SZ_16G,
938952
}
@@ -1193,6 +1207,7 @@ static const struct adreno_info a7xx_gpus[] = {
11931207
.a6xx = &(const struct a6xx_info) {
11941208
.hwcg = a702_hwcg,
11951209
.protect = &a650_protect,
1210+
.prim_fifo_threshold = 0x0000c000,
11961211
},
11971212
.speedbins = ADRENO_SPEEDBINS(
11981213
{ 0, 0 },

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 5 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -981,25 +981,11 @@ static int hw_init(struct msm_gpu *gpu)
981981
} else if (!adreno_is_a7xx(adreno_gpu))
982982
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
983983

984-
/* Setting the primFifo thresholds default values,
985-
* and vccCacheSkipDis=1 bit (0x200) for A640 and newer
986-
*/
987-
if (adreno_is_a702(adreno_gpu))
988-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000);
989-
else if (adreno_is_a690(adreno_gpu))
990-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200);
991-
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
992-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
993-
else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
994-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
995-
else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
996-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
997-
else if (adreno_is_a619(adreno_gpu))
998-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00018000);
999-
else if (adreno_is_a610(adreno_gpu))
1000-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00080000);
1001-
else if (!adreno_is_a7xx(adreno_gpu))
1002-
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
984+
985+
/* Set the default primFifo threshold values */
986+
if (adreno_gpu->info->a6xx->prim_fifo_threshold)
987+
gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL,
988+
adreno_gpu->info->a6xx->prim_fifo_threshold);
1003989

1004990
/* Set the AHB default slave response to "ERROR" */
1005991
gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ struct a6xx_info {
2222
const struct adreno_reglist *hwcg;
2323
const struct adreno_protect *protect;
2424
u32 gmu_chipid;
25+
u32 prim_fifo_threshold;
2526
};
2627

2728
struct a6xx_gpu {

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