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drm/xe: Initial MSI-X support for HW engines
- Configure the HW engines to work with MSI-X - Program the LRC to use memirq infra (similar to VF) - CS_INT_VEC field added to the LRC Bspec: 60342, 72547 Signed-off-by: Ilia Levi <ilia.levi@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20241213072538.6823-3-ilia.levi@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
1 parent da88907 commit 21d07f5

8 files changed

Lines changed: 44 additions & 11 deletions

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‎drivers/gpu/drm/xe/regs/xe_engine_regs.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,8 @@
8383
#define RING_IMR(base) XE_REG((base) + 0xa8)
8484
#define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac)
8585

86+
#define CS_INT_VEC(base) XE_REG((base) + 0x1b8)
87+
8688
#define RING_EIR(base) XE_REG((base) + 0xb0)
8789
#define RING_EMR(base) XE_REG((base) + 0xb4)
8890
#define RING_ESR(base) XE_REG((base) + 0xb8)
@@ -138,6 +140,7 @@
138140

139141
#define RING_MODE(base) XE_REG((base) + 0x29c)
140142
#define GFX_DISABLE_LEGACY_MODE REG_BIT(3)
143+
#define GFX_MSIX_INTERRUPT_ENABLE REG_BIT(13)
141144

142145
#define RING_TIMESTAMP(base) XE_REG((base) + 0x358)
143146

‎drivers/gpu/drm/xe/regs/xe_lrc_layout.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,9 @@
2525
#define CTX_INT_SRC_REPORT_REG (CTX_LRI_INT_REPORT_PTR + 3)
2626
#define CTX_INT_SRC_REPORT_PTR (CTX_LRI_INT_REPORT_PTR + 4)
2727

28+
#define CTX_CS_INT_VEC_REG 0x5a
29+
#define CTX_CS_INT_VEC_DATA (CTX_CS_INT_VEC_REG + 1)
30+
2831
#define INDIRECT_CTX_RING_HEAD (0x02 + 1)
2932
#define INDIRECT_CTX_RING_TAIL (0x04 + 1)
3033
#define INDIRECT_CTX_RING_START (0x06 + 1)

‎drivers/gpu/drm/xe/xe_exec_queue.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
#include "xe_hw_engine_class_sysfs.h"
1717
#include "xe_hw_engine_group.h"
1818
#include "xe_hw_fence.h"
19+
#include "xe_irq.h"
1920
#include "xe_lrc.h"
2021
#include "xe_macros.h"
2122
#include "xe_migrate.h"
@@ -68,6 +69,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
6869
q->gt = gt;
6970
q->class = hwe->class;
7071
q->width = width;
72+
q->msix_vec = XE_IRQ_DEFAULT_MSIX;
7173
q->logical_mask = logical_mask;
7274
q->fence_irq = &gt->fence_irq[hwe->class];
7375
q->ring_ops = gt->ring_ops[hwe->class];
@@ -117,7 +119,7 @@ static int __xe_exec_queue_init(struct xe_exec_queue *q)
117119
}
118120

119121
for (i = 0; i < q->width; ++i) {
120-
q->lrc[i] = xe_lrc_create(q->hwe, q->vm, SZ_16K);
122+
q->lrc[i] = xe_lrc_create(q->hwe, q->vm, SZ_16K, q->msix_vec);
121123
if (IS_ERR(q->lrc[i])) {
122124
err = PTR_ERR(q->lrc[i]);
123125
goto err_unlock;

‎drivers/gpu/drm/xe/xe_exec_queue_types.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,8 @@ struct xe_exec_queue {
6363
char name[MAX_FENCE_NAME_LEN];
6464
/** @width: width (number BB submitted per exec) of this exec queue */
6565
u16 width;
66+
/** @msix_vec: MSI-X vector (for platforms that support it) */
67+
u16 msix_vec;
6668
/** @fence_irq: fence IRQ used to signal job completion */
6769
struct xe_hw_fence_irq *fence_irq;
6870

‎drivers/gpu/drm/xe/xe_execlist.c‎

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@
1717
#include "xe_exec_queue.h"
1818
#include "xe_gt.h"
1919
#include "xe_hw_fence.h"
20+
#include "xe_irq.h"
2021
#include "xe_lrc.h"
2122
#include "xe_macros.h"
2223
#include "xe_mmio.h"
@@ -47,6 +48,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
4748
struct xe_mmio *mmio = &gt->mmio;
4849
struct xe_device *xe = gt_to_xe(gt);
4950
u64 lrc_desc;
51+
u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE);
5052

5153
lrc_desc = xe_lrc_descriptor(lrc);
5254

@@ -80,8 +82,10 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc,
8082
xe_mmio_write32(mmio, RING_HWS_PGA(hwe->mmio_base),
8183
xe_bo_ggtt_addr(hwe->hwsp));
8284
xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base));
83-
xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base),
84-
_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
85+
86+
if (xe_device_has_msix(gt_to_xe(hwe->gt)))
87+
ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
88+
xe_mmio_write32(mmio, RING_MODE(hwe->mmio_base), ring_mode);
8589

8690
xe_mmio_write32(mmio, RING_EXECLIST_SQ_CONTENTS_LO(hwe->mmio_base),
8791
lower_32_bits(lrc_desc));
@@ -265,7 +269,7 @@ struct xe_execlist_port *xe_execlist_port_create(struct xe_device *xe,
265269

266270
port->hwe = hwe;
267271

268-
port->lrc = xe_lrc_create(hwe, NULL, SZ_16K);
272+
port->lrc = xe_lrc_create(hwe, NULL, SZ_16K, XE_IRQ_DEFAULT_MSIX);
269273
if (IS_ERR(port->lrc)) {
270274
err = PTR_ERR(port->lrc);
271275
goto err;

‎drivers/gpu/drm/xe/xe_hw_engine.c‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -324,6 +324,7 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
324324
{
325325
u32 ccs_mask =
326326
xe_hw_engine_mask_per_class(hwe->gt, XE_ENGINE_CLASS_COMPUTE);
327+
u32 ring_mode = _MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE);
327328

328329
if (hwe->class == XE_ENGINE_CLASS_COMPUTE && ccs_mask)
329330
xe_mmio_write32(&hwe->gt->mmio, RCU_MODE,
@@ -332,8 +333,10 @@ void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
332333
xe_hw_engine_mmio_write32(hwe, RING_HWSTAM(0), ~0x0);
333334
xe_hw_engine_mmio_write32(hwe, RING_HWS_PGA(0),
334335
xe_bo_ggtt_addr(hwe->hwsp));
335-
xe_hw_engine_mmio_write32(hwe, RING_MODE(0),
336-
_MASKED_BIT_ENABLE(GFX_DISABLE_LEGACY_MODE));
336+
337+
if (xe_device_has_msix(gt_to_xe(hwe->gt)))
338+
ring_mode |= _MASKED_BIT_ENABLE(GFX_MSIX_INTERRUPT_ENABLE);
339+
xe_hw_engine_mmio_write32(hwe, RING_MODE(0), ring_mode);
337340
xe_hw_engine_mmio_write32(hwe, RING_MI_MODE(0),
338341
_MASKED_BIT_DISABLE(STOP_RING));
339342
xe_hw_engine_mmio_read32(hwe, RING_MI_MODE(0));

‎drivers/gpu/drm/xe/xe_lrc.c‎

Lines changed: 20 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -584,6 +584,7 @@ static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
584584
{
585585
struct xe_memirq *memirq = &gt_to_tile(hwe->gt)->memirq;
586586
struct xe_device *xe = gt_to_xe(hwe->gt);
587+
u8 num_regs;
587588

588589
if (!xe_device_uses_memirq(xe))
589590
return;
@@ -593,12 +594,18 @@ static void set_memory_based_intr(u32 *regs, struct xe_hw_engine *hwe)
593594
regs[CTX_INT_MASK_ENABLE_REG] = RING_IMR(0).addr;
594595
regs[CTX_INT_MASK_ENABLE_PTR] = xe_memirq_enable_ptr(memirq);
595596

596-
regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(2) |
597+
num_regs = xe_device_has_msix(xe) ? 3 : 2;
598+
regs[CTX_LRI_INT_REPORT_PTR] = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(num_regs) |
597599
MI_LRI_LRM_CS_MMIO | MI_LRI_FORCE_POSTED;
598600
regs[CTX_INT_STATUS_REPORT_REG] = RING_INT_STATUS_RPT_PTR(0).addr;
599601
regs[CTX_INT_STATUS_REPORT_PTR] = xe_memirq_status_ptr(memirq, hwe);
600602
regs[CTX_INT_SRC_REPORT_REG] = RING_INT_SRC_RPT_PTR(0).addr;
601603
regs[CTX_INT_SRC_REPORT_PTR] = xe_memirq_source_ptr(memirq, hwe);
604+
605+
if (xe_device_has_msix(xe)) {
606+
regs[CTX_CS_INT_VEC_REG] = CS_INT_VEC(0).addr;
607+
/* CTX_CS_INT_VEC_DATA will be set in xe_lrc_init */
608+
}
602609
}
603610

604611
static int lrc_ring_mi_mode(struct xe_hw_engine *hwe)
@@ -876,7 +883,7 @@ static void xe_lrc_finish(struct xe_lrc *lrc)
876883
#define PVC_CTX_ACC_CTR_THOLD (0x2a + 1)
877884

878885
static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
879-
struct xe_vm *vm, u32 ring_size)
886+
struct xe_vm *vm, u32 ring_size, u16 msix_vec)
880887
{
881888
struct xe_gt *gt = hwe->gt;
882889
struct xe_tile *tile = gt_to_tile(gt);
@@ -945,6 +952,14 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
945952
xe_drm_client_add_bo(vm->xef->client, lrc->bo);
946953
}
947954

955+
if (xe_device_has_msix(xe)) {
956+
xe_lrc_write_ctx_reg(lrc, CTX_INT_STATUS_REPORT_PTR,
957+
xe_memirq_status_ptr(&tile->memirq, hwe));
958+
xe_lrc_write_ctx_reg(lrc, CTX_INT_SRC_REPORT_PTR,
959+
xe_memirq_source_ptr(&tile->memirq, hwe));
960+
xe_lrc_write_ctx_reg(lrc, CTX_CS_INT_VEC_DATA, msix_vec << 16 | msix_vec);
961+
}
962+
948963
if (xe_gt_has_indirect_ring_state(gt)) {
949964
xe_lrc_write_ctx_reg(lrc, CTX_INDIRECT_RING_STATE,
950965
__xe_lrc_indirect_ring_ggtt_addr(lrc));
@@ -1005,14 +1020,15 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe,
10051020
* @hwe: Hardware Engine
10061021
* @vm: The VM (address space)
10071022
* @ring_size: LRC ring size
1023+
* @msix_vec: MSI-X interrupt vector (for platforms that support it)
10081024
*
10091025
* Allocate and initialize the Logical Ring Context (LRC).
10101026
*
10111027
* Return pointer to created LRC upon success and an error pointer
10121028
* upon failure.
10131029
*/
10141030
struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
1015-
u32 ring_size)
1031+
u32 ring_size, u16 msix_vec)
10161032
{
10171033
struct xe_lrc *lrc;
10181034
int err;
@@ -1021,7 +1037,7 @@ struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
10211037
if (!lrc)
10221038
return ERR_PTR(-ENOMEM);
10231039

1024-
err = xe_lrc_init(lrc, hwe, vm, ring_size);
1040+
err = xe_lrc_init(lrc, hwe, vm, ring_size, msix_vec);
10251041
if (err) {
10261042
kfree(lrc);
10271043
return ERR_PTR(err);

‎drivers/gpu/drm/xe/xe_lrc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ struct xe_lrc_snapshot {
4242
#define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4)
4343

4444
struct xe_lrc *xe_lrc_create(struct xe_hw_engine *hwe, struct xe_vm *vm,
45-
u32 ring_size);
45+
u32 ring_size, u16 msix_vec);
4646
void xe_lrc_destroy(struct kref *ref);
4747

4848
/**

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