Skip to content

Commit 1d341e5

Browse files
captain5050namhyung
authored andcommitted
perf vendor events intel: Update graniterapids events from 1.15 to 1.16
The updated events were published in: intel/perfmon@b4acc3f Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org>
1 parent 5a341cc commit 1d341e5

3 files changed

Lines changed: 12 additions & 3 deletions

File tree

tools/perf/pmu-events/arch/x86/graniterapids/cache.json

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -488,12 +488,12 @@
488488
"UMask": "0x2"
489489
},
490490
{
491-
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
491+
"BriefDescription": "Retired load instructions which data sources missed L3 but serviced from dram homed in the local socket",
492492
"Counter": "0,1,2,3",
493493
"Data_LA": "1",
494494
"EventCode": "0xd3",
495495
"EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
496-
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM. Available PDIST counters: 0",
496+
"PublicDescription": "Retired load instructions which data sources missed L3 but serviced from DRAM homed in the local socket. Available PDIST counters: 0",
497497
"RetirementLatencyMax": 4146,
498498
"RetirementLatencyMean": 115.83,
499499
"RetirementLatencyMin": 0,

tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,15 @@
99
"PublicDescription": "UNC_CHACMS_CLOCKTICKS",
1010
"Unit": "CHACMS"
1111
},
12+
{
13+
"BriefDescription": "UNC_CHACMS_DISTRESS_ASSERTED",
14+
"Counter": "0,1,2,3",
15+
"EventCode": "0x35",
16+
"EventName": "UNC_CHACMS_DISTRESS_ASSERTED",
17+
"PerPkg": "1",
18+
"PortMask": "0x000",
19+
"Unit": "CHACMS"
20+
},
1221
{
1322
"BriefDescription": "Counts the number of cycles FAST trigger is received from the global FAST distress wire.",
1423
"Counter": "0,1,2,3",

tools/perf/pmu-events/arch/x86/mapfile.csv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.20,emeraldrapids,core
1313
GenuineIntel-6-5[CF],v13,goldmont,core
1414
GenuineIntel-6-7A,v1.01,goldmontplus,core
1515
GenuineIntel-6-B6,v1.10,grandridge,core
16-
GenuineIntel-6-A[DE],v1.15,graniterapids,core
16+
GenuineIntel-6-A[DE],v1.16,graniterapids,core
1717
GenuineIntel-6-(3C|45|46),v36,haswell,core
1818
GenuineIntel-6-3F,v29,haswellx,core
1919
GenuineIntel-6-7[DE],v1.24,icelake,core

0 commit comments

Comments
 (0)