drm/msm: Drop msm_read/writel

konradybcio · lumag · commit 0efadfb0050e · 2024-04-22T16:22:50.000+03:00
Totally useless. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Patchwork: https://patchwork.freedesktop.org/patch/588804/ Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -507,7 +507,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
 
 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
 {
-	msm_writel(value, ptr + (offset << 2));
+	writel(value, ptr + (offset << 2));
 }
 
 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.h
@@ -103,12 +103,12 @@ struct a6xx_gmu {
 
 static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
 {
-	return msm_readl(gmu->mmio + (offset << 2));
+	return readl(gmu->mmio + (offset << 2));
 }
 
 static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
 {
-	msm_writel(value, gmu->mmio + (offset << 2));
+	writel(value, gmu->mmio + (offset << 2));
 }
 
 static inline void
@@ -131,8 +131,8 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 {
 	u64 val;
 
-	val = (u64) msm_readl(gmu->mmio + (lo << 2));
-	val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
+	val = (u64) readl(gmu->mmio + (lo << 2));
+	val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
 
 	return val;
 }
@@ -143,12 +143,12 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
 
 static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
 {
-	return msm_readl(gmu->rscc + (offset << 2));
+	return readl(gmu->rscc + (offset << 2));
 }
 
 static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
 {
-	msm_writel(value, gmu->rscc + (offset << 2));
+	writel(value, gmu->rscc + (offset << 2));
 }
 
 #define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -69,12 +69,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3
 
 static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
 {
-	return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
+	return readl(a6xx_gpu->llc_mmio + (reg << 2));
 }
 
 static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
 {
-	msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+	writel(value, a6xx_gpu->llc_mmio + (reg << 2));
 }
 
 #define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
@@ -192,10 +192,10 @@ static int debugbus_read(struct msm_gpu *gpu, u32 block, u32 offset,
 }
 
 #define cxdbg_write(ptr, offset, val) \
-	msm_writel((val), (ptr) + ((offset) << 2))
+	writel((val), (ptr) + ((offset) << 2))
 
 #define cxdbg_read(ptr, offset) \
-	msm_readl((ptr) + ((offset) << 2))
+	readl((ptr) + ((offset) << 2))
 
 /* read a value from the CX debug bus */
 static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h b/drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
@@ -44,12 +44,12 @@ struct mdp4_kms {
 
 static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
 {
-	msm_writel(data, mdp4_kms->mmio + reg);
+	writel(data, mdp4_kms->mmio + reg);
 }
 
 static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
 {
-	return msm_readl(mdp4_kms->mmio + reg);
+	return readl(mdp4_kms->mmio + reg);
 }
 
 static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
@@ -171,13 +171,13 @@ struct mdp5_encoder {
 static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
 {
 	WARN_ON(mdp5_kms->enable_count <= 0);
-	msm_writel(data, mdp5_kms->mmio + reg);
+	writel(data, mdp5_kms->mmio + reg);
 }
 
 static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
 {
 	WARN_ON(mdp5_kms->enable_count <= 0);
-	return msm_readl(mdp5_kms->mmio + reg);
+	return readl(mdp5_kms->mmio + reg);
 }
 
 static inline const char *stage2name(enum mdp_mixer_stage_id stage)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -55,7 +55,7 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
 	 * scratch register which we never touch)
 	 */
 
-	ver = msm_readl(base + REG_DSI_VERSION);
+	ver = readl(base + REG_DSI_VERSION);
 	if (ver) {
 		/* older dsi host, there is no register shift */
 		ver = FIELD(ver, DSI_VERSION_MAJOR);
@@ -73,12 +73,12 @@ static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
 		 * registers are shifted down, read DSI_VERSION again with
 		 * the shifted offset
 		 */
-		ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
+		ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
 		ver = FIELD(ver, DSI_VERSION_MAJOR);
 		if (ver == MSM_DSI_VER_MAJOR_6G) {
 			/* 6G version */
 			*major = ver;
-			*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
+			*minor = readl(base + REG_DSI_6G_HW_VERSION);
 			return 0;
 		} else {
 			return -EINVAL;
@@ -186,11 +186,11 @@ struct msm_dsi_host {
 
 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
 {
-	return msm_readl(msm_host->ctrl_base + reg);
+	return readl(msm_host->ctrl_base + reg);
 }
 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
 {
-	msm_writel(data, msm_host->ctrl_base + reg);
+	writel(data, msm_host->ctrl_base + reg);
 }
 
 static const struct msm_dsi_cfg_handler *dsi_get_config(
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -12,10 +12,10 @@
 
 #include "dsi.h"
 
-#define dsi_phy_read(offset) msm_readl((offset))
-#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
-#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
+#define dsi_phy_read(offset) readl((offset))
+#define dsi_phy_write(offset, data) writel((data), (offset))
+#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
+#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
 
 struct msm_dsi_phy_ops {
 	int (*pll_init)(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h
@@ -115,17 +115,17 @@ void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
 
 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
 {
-	msm_writel(data, hdmi->mmio + reg);
+	writel(data, hdmi->mmio + reg);
 }
 
 static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
 {
-	return msm_readl(hdmi->mmio + reg);
+	return readl(hdmi->mmio + reg);
 }
 
 static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
 {
-	return msm_readl(hdmi->qfprom_mmio + reg);
+	return readl(hdmi->qfprom_mmio + reg);
 }
 
 /*
@@ -166,12 +166,12 @@ struct hdmi_phy {
 
 static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
 {
-	msm_writel(data, phy->mmio + reg);
+	writel(data, phy->mmio + reg);
 }
 
 static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
 {
-	return msm_readl(phy->mmio + reg);
+	return readl(phy->mmio + reg);
 }
 
 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
@@ -86,18 +86,18 @@ static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll)
 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
 				  u32 data)
 {
-	msm_writel(data, pll->mmio_qserdes_com + offset);
+	writel(data, pll->mmio_qserdes_com + offset);
 }
 
 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
 {
-	return msm_readl(pll->mmio_qserdes_com + offset);
+	return readl(pll->mmio_qserdes_com + offset);
 }
 
 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
 				      int offset, int data)
 {
-	 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
+	 writel(data, pll->mmio_qserdes_tx[channel] + offset);
 }
 
 static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
@@ -236,12 +236,12 @@ static const struct pll_rate freqtbl[] = {
 
 static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
 {
-	msm_writel(data, pll->mmio + reg);
+	writel(data, pll->mmio + reg);
 }
 
 static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
 {
-	return msm_readl(pll->mmio + reg);
+	return readl(pll->mmio + reg);
 }
 
 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
@@ -488,15 +488,12 @@ void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev,
 
 struct icc_path *msm_icc_get(struct device *dev, const char *name);
 
-#define msm_writel(data, addr) writel((data), (addr))
-#define msm_readl(addr) readl((addr))
-
 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
 {
-	u32 val = msm_readl(addr);
+	u32 val = readl(addr);
 
 	val &= ~mask;
-	msm_writel(val | or, addr);
+	writel(val | or, addr);
 }
 
 /**
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
@@ -555,12 +555,12 @@ struct msm_gpu_state {
 
 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
 {
-	msm_writel(data, gpu->mmio + (reg << 2));
+	writel(data, gpu->mmio + (reg << 2));
 }
 
 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
 {
-	return msm_readl(gpu->mmio + (reg << 2));
+	return readl(gpu->mmio + (reg << 2));
 }
 
 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
@@ -586,17 +586,17 @@ static inline u64 gpu_read64(struct msm_gpu *gpu, u32 reg)
 	 * when the lo is read, so make sure to read the lo first to trigger
 	 * that
 	 */
-	val = (u64) msm_readl(gpu->mmio + (reg << 2));
-	val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
+	val = (u64) readl(gpu->mmio + (reg << 2));
+	val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
 
 	return val;
 }
 
 static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
 {
 	/* Why not a writeq here? Read the screed above */
-	msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
-	msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
+	writel(lower_32_bits(val), gpu->mmio + (reg << 2));
+	writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
 }
 
 int msm_gpu_pm_suspend(struct msm_gpu *gpu);

Original file line number	Diff line number	Diff line change
`@@ -507,7 +507,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)`
`507`	`507`
`508`	`508`	`static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)`
`509`	`509`	`{`
`510`		`- msm_writel(value, ptr + (offset << 2));`
	`510`	`+ writel(value, ptr + (offset << 2));`
`511`	`511`	`}`
`512`	`512`
`513`	`513`	`static void __iomem a6xx_gmu_get_mmio(struct platform_device pdev,`
Original file line number	Diff line number	Diff line change
`@@ -103,12 +103,12 @@ struct a6xx_gmu {`
`103`	`103`
`104`	`104`	`static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)`
`105`	`105`	`{`
`106`		`- return msm_readl(gmu->mmio + (offset << 2));`
	`106`	`+ return readl(gmu->mmio + (offset << 2));`
`107`	`107`	`}`
`108`	`108`
`109`	`109`	`static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)`
`110`	`110`	`{`
`111`		`- msm_writel(value, gmu->mmio + (offset << 2));`
	`111`	`+ writel(value, gmu->mmio + (offset << 2));`
`112`	`112`	`}`
`113`	`113`
`114`	`114`	`static inline void`
`@@ -131,8 +131,8 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)`
`131`	`131`	`{`
`132`	`132`	`u64 val;`
`133`	`133`
`134`		`- val = (u64) msm_readl(gmu->mmio + (lo << 2));`
`135`		`- val \|= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);`
	`134`	`+ val = (u64) readl(gmu->mmio + (lo << 2));`
	`135`	`+ val \|= ((u64) readl(gmu->mmio + (hi << 2)) << 32);`
`136`	`136`
`137`	`137`	`return val;`
`138`	`138`	`}`
`@@ -143,12 +143,12 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)`
`143`	`143`
`144`	`144`	`static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)`
`145`	`145`	`{`
`146`		`- return msm_readl(gmu->rscc + (offset << 2));`
	`146`	`+ return readl(gmu->rscc + (offset << 2));`
`147`	`147`	`}`
`148`	`148`
`149`	`149`	`static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)`
`150`	`150`	`{`
`151`		`- msm_writel(value, gmu->rscc + (offset << 2));`
	`151`	`+ writel(value, gmu->rscc + (offset << 2));`
`152`	`152`	`}`
`153`	`153`
`154`	`154`	`#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \`
Original file line number	Diff line number	Diff line change
`@@ -69,12 +69,12 @@ static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u3`
`69`	`69`
`70`	`70`	`static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)`
`71`	`71`	`{`
`72`		`- return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));`
	`72`	`+ return readl(a6xx_gpu->llc_mmio + (reg << 2));`
`73`	`73`	`}`
`74`	`74`
`75`	`75`	`static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)`
`76`	`76`	`{`
`77`		`- msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));`
	`77`	`+ writel(value, a6xx_gpu->llc_mmio + (reg << 2));`
`78`	`78`	`}`
`79`	`79`
`80`	`80`	`#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \`
Original file line number	Diff line number	Diff line change
`@@ -44,12 +44,12 @@ struct mdp4_kms {`
`44`	`44`
`45`	`45`	`static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)`
`46`	`46`	`{`
`47`		`- msm_writel(data, mdp4_kms->mmio + reg);`
	`47`	`+ writel(data, mdp4_kms->mmio + reg);`
`48`	`48`	`}`
`49`	`49`
`50`	`50`	`static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)`
`51`	`51`	`{`
`52`		`- return msm_readl(mdp4_kms->mmio + reg);`
	`52`	`+ return readl(mdp4_kms->mmio + reg);`
`53`	`53`	`}`
`54`	`54`
`55`	`55`	`static inline uint32_t pipe2flush(enum mdp4_pipe pipe)`
Original file line number	Diff line number	Diff line change
`@@ -171,13 +171,13 @@ struct mdp5_encoder {`
`171`	`171`	`static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)`
`172`	`172`	`{`
`173`	`173`	`WARN_ON(mdp5_kms->enable_count <= 0);`
`174`		`- msm_writel(data, mdp5_kms->mmio + reg);`
	`174`	`+ writel(data, mdp5_kms->mmio + reg);`
`175`	`175`	`}`
`176`	`176`
`177`	`177`	`static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)`
`178`	`178`	`{`
`179`	`179`	`WARN_ON(mdp5_kms->enable_count <= 0);`
`180`		`- return msm_readl(mdp5_kms->mmio + reg);`
	`180`	`+ return readl(mdp5_kms->mmio + reg);`
`181`	`181`	`}`
`182`	`182`
`183`	`183`	`static inline const char *stage2name(enum mdp_mixer_stage_id stage)`
Original file line number	Diff line number	Diff line change
`@@ -115,17 +115,17 @@ void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);`
`115`	`115`
`116`	`116`	`static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)`
`117`	`117`	`{`
`118`		`- msm_writel(data, hdmi->mmio + reg);`
	`118`	`+ writel(data, hdmi->mmio + reg);`
`119`	`119`	`}`
`120`	`120`
`121`	`121`	`static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)`
`122`	`122`	`{`
`123`		`- return msm_readl(hdmi->mmio + reg);`
	`123`	`+ return readl(hdmi->mmio + reg);`
`124`	`124`	`}`
`125`	`125`
`126`	`126`	`static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)`
`127`	`127`	`{`
`128`		`- return msm_readl(hdmi->qfprom_mmio + reg);`
	`128`	`+ return readl(hdmi->qfprom_mmio + reg);`
`129`	`129`	`}`
`130`	`130`
`131`	`131`	`/*`
`@@ -166,12 +166,12 @@ struct hdmi_phy {`
`166`	`166`
`167`	`167`	`static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)`
`168`	`168`	`{`
`169`		`- msm_writel(data, phy->mmio + reg);`
	`169`	`+ writel(data, phy->mmio + reg);`
`170`	`170`	`}`
`171`	`171`
`172`	`172`	`static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)`
`173`	`173`	`{`
`174`		`- return msm_readl(phy->mmio + reg);`
	`174`	`+ return readl(phy->mmio + reg);`
`175`	`175`	`}`
`176`	`176`
`177`	`177`	`int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);`
Original file line number	Diff line number	Diff line change
`@@ -86,18 +86,18 @@ static inline struct hdmi_phy pll_get_phy(struct hdmi_pll_8996 pll)`
`86`	`86`	`static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,`
`87`	`87`	`u32 data)`
`88`	`88`	`{`
`89`		`- msm_writel(data, pll->mmio_qserdes_com + offset);`
	`89`	`+ writel(data, pll->mmio_qserdes_com + offset);`
`90`	`90`	`}`
`91`	`91`
`92`	`92`	`static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)`
`93`	`93`	`{`
`94`		`- return msm_readl(pll->mmio_qserdes_com + offset);`
	`94`	`+ return readl(pll->mmio_qserdes_com + offset);`
`95`	`95`	`}`
`96`	`96`
`97`	`97`	`static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,`
`98`	`98`	`int offset, int data)`
`99`	`99`	`{`
`100`		`- msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);`
	`100`	`+ writel(data, pll->mmio_qserdes_tx[channel] + offset);`
`101`	`101`	`}`
`102`	`102`
`103`	`103`	`static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,`