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drm/i915/de: Use intel_de_wait_for_{set,clear}_us()
Use intel_de_wait_for_{set,clear}_us() instead of intel_de_wait_us() where appropriate. Done with cocci (with manual formatting fixes): @@ identifier func !~ "intel_de_wait_for"; expression display, reg, mask, timeout_us; @@ func(...) { <... ( - intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL) + intel_de_wait_for_set_us(display, reg, mask, timeout_us) | - intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL) + intel_de_wait_for_clear_us(display, reg, mask, timeout_us) ) ...> } Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-10-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
1 parent 58a43c9 commit 0aed9d3

8 files changed

Lines changed: 57 additions & 59 deletions

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‎drivers/gpu/drm/i915/display/icl_dsi.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -148,8 +148,9 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
148148
for_each_dsi_port(port, intel_dsi->ports) {
149149
dsi_trans = dsi_port_to_transcoder(port);
150150

151-
ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
152-
LPTX_IN_PROGRESS, 0, 20, NULL);
151+
ret = intel_de_wait_for_clear_us(display,
152+
DSI_LP_MSG(dsi_trans),
153+
LPTX_IN_PROGRESS, 20);
153154
if (ret)
154155
drm_err(display->drm, "LPTX bit not cleared\n");
155156
}
@@ -533,8 +534,8 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
533534
for_each_dsi_port(port, intel_dsi->ports) {
534535
intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
535536

536-
ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
537-
DDI_BUF_IS_IDLE, 0, 500, NULL);
537+
ret = intel_de_wait_for_clear_us(display, DDI_BUF_CTL(port),
538+
DDI_BUF_IS_IDLE, 500);
538539
if (ret)
539540
drm_err(display->drm, "DDI port:%c buffer idle\n",
540541
port_name(port));
@@ -855,9 +856,9 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
855856

856857
dsi_trans = dsi_port_to_transcoder(port);
857858

858-
ret = intel_de_wait_us(display,
859-
DSI_TRANS_FUNC_CONF(dsi_trans),
860-
LINK_READY, LINK_READY, 2500, NULL);
859+
ret = intel_de_wait_for_set_us(display,
860+
DSI_TRANS_FUNC_CONF(dsi_trans),
861+
LINK_READY, 2500);
861862
if (ret)
862863
drm_err(display->drm, "DSI link not ready\n");
863864
}
@@ -1356,8 +1357,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
13561357
tmp &= ~LINK_ULPS_TYPE_LP11;
13571358
intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
13581359

1359-
ret = intel_de_wait_us(display, DSI_LP_MSG(dsi_trans),
1360-
LINK_IN_ULPS, LINK_IN_ULPS, 10, NULL);
1360+
ret = intel_de_wait_for_set_us(display, DSI_LP_MSG(dsi_trans),
1361+
LINK_IN_ULPS, 10);
13611362
if (ret)
13621363
drm_err(display->drm, "DSI link not in ULPS\n");
13631364
}
@@ -1392,9 +1393,8 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
13921393
for_each_dsi_port(port, intel_dsi->ports) {
13931394
intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
13941395

1395-
ret = intel_de_wait_us(display, DDI_BUF_CTL(port),
1396-
DDI_BUF_IS_IDLE, DDI_BUF_IS_IDLE, 8,
1397-
NULL);
1396+
ret = intel_de_wait_for_set_us(display, DDI_BUF_CTL(port),
1397+
DDI_BUF_IS_IDLE, 8);
13981398

13991399
if (ret)
14001400
drm_err(display->drm,

‎drivers/gpu/drm/i915/display/intel_cdclk.c‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -902,8 +902,8 @@ static void bdw_set_cdclk(struct intel_display *display,
902902
* According to the spec, it should be enough to poll for this 1 us.
903903
* However, extensive testing shows that this can take longer.
904904
*/
905-
ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
906-
LCPLL_CD_SOURCE_FCLK_DONE, 100, NULL);
905+
ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
906+
LCPLL_CD_SOURCE_FCLK_DONE, 100);
907907
if (ret)
908908
drm_err(display->drm, "Switching to FCLK failed\n");
909909

@@ -913,8 +913,8 @@ static void bdw_set_cdclk(struct intel_display *display,
913913
intel_de_rmw(display, LCPLL_CTL,
914914
LCPLL_CD_SOURCE_FCLK, 0);
915915

916-
ret = intel_de_wait_us(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK_DONE,
917-
0, 1, NULL);
916+
ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
917+
LCPLL_CD_SOURCE_FCLK_DONE, 1);
918918
if (ret)
919919
drm_err(display->drm, "Switching back to LCPLL failed\n");
920920

‎drivers/gpu/drm/i915/display/intel_cx0_phy.c‎

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -2887,20 +2887,19 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
28872887
XELPDP_LANE_PHY_CURRENT_STATUS(1))
28882888
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
28892889

2890-
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL1(display, port),
2891-
XELPDP_PORT_BUF_SOC_PHY_READY,
2892-
XELPDP_PORT_BUF_SOC_PHY_READY,
2893-
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, NULL))
2890+
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL1(display, port),
2891+
XELPDP_PORT_BUF_SOC_PHY_READY,
2892+
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US))
28942893
drm_warn(display->drm,
28952894
"PHY %c failed to bring out of SOC reset\n",
28962895
phy_name(phy));
28972896

28982897
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
28992898
lane_pipe_reset);
29002899

2901-
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2902-
lane_phy_current_status, lane_phy_current_status,
2903-
XELPDP_PORT_RESET_START_TIMEOUT_US, NULL))
2900+
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2901+
lane_phy_current_status,
2902+
XELPDP_PORT_RESET_START_TIMEOUT_US))
29042903
drm_warn(display->drm,
29052904
"PHY %c failed to bring out of lane reset\n",
29062905
phy_name(phy));
@@ -3187,8 +3186,8 @@ void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
31873186
intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
31883187

31893188
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
3190-
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3191-
XELPDP_TBT_CLOCK_ACK, XELPDP_TBT_CLOCK_ACK, 100, NULL))
3189+
if (intel_de_wait_for_set_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3190+
XELPDP_TBT_CLOCK_ACK, 100))
31923191
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked\n",
31933192
encoder->base.base.id, encoder->base.name, phy_name(phy));
31943193

@@ -3299,10 +3298,10 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
32993298
/*
33003299
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
33013300
*/
3302-
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3303-
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
3304-
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
3305-
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, NULL))
3301+
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3302+
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
3303+
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES),
3304+
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US))
33063305
drm_warn(display->drm, "Port %c PLL not unlocked\n",
33073306
phy_name(phy));
33083307

@@ -3347,8 +3346,8 @@ void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
33473346
XELPDP_TBT_CLOCK_REQUEST, 0);
33483347

33493348
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
3350-
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3351-
XELPDP_TBT_CLOCK_ACK, 0, 10, NULL))
3349+
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
3350+
XELPDP_TBT_CLOCK_ACK, 10))
33523351
drm_warn(display->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked\n",
33533352
encoder->base.base.id, encoder->base.name, phy_name(phy));
33543353

‎drivers/gpu/drm/i915/display/intel_ddi.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2577,7 +2577,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
25772577

25782578
intel_de_rmw(display, reg, 0, set_bits);
25792579

2580-
ret = intel_de_wait_us(display, reg, wait_bits, wait_bits, 100, NULL);
2580+
ret = intel_de_wait_for_set_us(display, reg, wait_bits, 100);
25812581
if (ret) {
25822582
drm_err(display->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
25832583
port_name(port));
@@ -3077,7 +3077,7 @@ mtl_ddi_disable_d2d(struct intel_encoder *encoder)
30773077

30783078
intel_de_rmw(display, reg, clr_bits, 0);
30793079

3080-
ret = intel_de_wait_us(display, reg, wait_bits, 0, 100, NULL);
3080+
ret = intel_de_wait_for_clear_us(display, reg, wait_bits, 100);
30813081
if (ret)
30823082
drm_err(display->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
30833083
port_name(port));

‎drivers/gpu/drm/i915/display/intel_display_power.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1292,9 +1292,8 @@ static void hsw_disable_lcpll(struct intel_display *display,
12921292
val |= LCPLL_CD_SOURCE_FCLK;
12931293
intel_de_write(display, LCPLL_CTL, val);
12941294

1295-
ret = intel_de_wait_us(display, LCPLL_CTL,
1296-
LCPLL_CD_SOURCE_FCLK_DONE,
1297-
LCPLL_CD_SOURCE_FCLK_DONE, 1, NULL);
1295+
ret = intel_de_wait_for_set_us(display, LCPLL_CTL,
1296+
LCPLL_CD_SOURCE_FCLK_DONE, 1);
12981297
if (ret)
12991298
drm_err(display->drm, "Switching to FCLK failed\n");
13001299

@@ -1368,8 +1367,8 @@ static void hsw_restore_lcpll(struct intel_display *display)
13681367
if (val & LCPLL_CD_SOURCE_FCLK) {
13691368
intel_de_rmw(display, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0);
13701369

1371-
ret = intel_de_wait_us(display, LCPLL_CTL,
1372-
LCPLL_CD_SOURCE_FCLK_DONE, 0, 1, NULL);
1370+
ret = intel_de_wait_for_clear_us(display, LCPLL_CTL,
1371+
LCPLL_CD_SOURCE_FCLK_DONE, 1);
13731372
if (ret)
13741373
drm_err(display->drm,
13751374
"Switching back to LCPLL failed\n");

‎drivers/gpu/drm/i915/display/intel_dpll_mgr.c‎

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2057,9 +2057,9 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
20572057
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
20582058
0, PORT_PLL_POWER_ENABLE);
20592059

2060-
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2061-
PORT_PLL_POWER_STATE,
2062-
PORT_PLL_POWER_STATE, 200, NULL);
2060+
ret = intel_de_wait_for_set_us(display,
2061+
BXT_PORT_PLL_ENABLE(port),
2062+
PORT_PLL_POWER_STATE, 200);
20632063
if (ret)
20642064
drm_err(display->drm,
20652065
"Power state not set for PLL:%d\n", port);
@@ -2122,8 +2122,8 @@ static void bxt_ddi_pll_enable(struct intel_display *display,
21222122
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
21232123
intel_de_posting_read(display, BXT_PORT_PLL_ENABLE(port));
21242124

2125-
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2126-
PORT_PLL_LOCK, PORT_PLL_LOCK, 200, NULL);
2125+
ret = intel_de_wait_for_set_us(display, BXT_PORT_PLL_ENABLE(port),
2126+
PORT_PLL_LOCK, 200);
21272127
if (ret)
21282128
drm_err(display->drm, "PLL %d not locked\n", port);
21292129

@@ -2157,8 +2157,9 @@ static void bxt_ddi_pll_disable(struct intel_display *display,
21572157
intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port),
21582158
PORT_PLL_POWER_ENABLE, 0);
21592159

2160-
ret = intel_de_wait_us(display, BXT_PORT_PLL_ENABLE(port),
2161-
PORT_PLL_POWER_STATE, 0, 200, NULL);
2160+
ret = intel_de_wait_for_clear_us(display,
2161+
BXT_PORT_PLL_ENABLE(port),
2162+
PORT_PLL_POWER_STATE, 200);
21622163
if (ret)
21632164
drm_err(display->drm,
21642165
"Power state not reset for PLL:%d\n", port);

‎drivers/gpu/drm/i915/display/intel_lt_phy.c‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1981,9 +1981,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
19811981
XELPDP_LANE_PCLK_PLL_REQUEST(0), 0);
19821982

19831983
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
1984-
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
1985-
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
1986-
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
1984+
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
1985+
XELPDP_LANE_PCLK_PLL_ACK(0),
1986+
XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
19871987
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
19881988
phy_name(phy));
19891989

@@ -2087,9 +2087,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
20872087
lane_pipe_reset);
20882088

20892089
/* 3. Poll for PORT_BUF_CTL2<port> Lane<PHY Lanes Owned> PHY Current Status == 1. */
2090-
if (intel_de_wait_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2091-
lane_phy_current_status, lane_phy_current_status,
2092-
XE3PLPD_RESET_START_LATENCY_US, NULL))
2090+
if (intel_de_wait_for_set_us(display, XELPDP_PORT_BUF_CTL2(display, port),
2091+
lane_phy_current_status,
2092+
XE3PLPD_RESET_START_LATENCY_US))
20932093
drm_warn(display->drm, "PHY %c failed to reset lane\n",
20942094
phy_name(phy));
20952095

@@ -2110,9 +2110,9 @@ void intel_lt_phy_pll_disable(struct intel_encoder *encoder)
21102110
intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
21112111

21122112
/* 8. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 0. */
2113-
if (intel_de_wait_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
2114-
XELPDP_LANE_PCLK_PLL_ACK(0), 0,
2115-
XE3PLPD_MACCLK_TURNOFF_LATENCY_US, NULL))
2113+
if (intel_de_wait_for_clear_us(display, XELPDP_PORT_CLOCK_CTL(display, port),
2114+
XELPDP_LANE_PCLK_PLL_ACK(0),
2115+
XE3PLPD_MACCLK_TURNOFF_LATENCY_US))
21162116
drm_warn(display->drm, "PHY %c PLL MacCLK ack deassertion timeout\n",
21172117
phy_name(phy));
21182118

‎drivers/gpu/drm/i915/display/intel_pch_refclk.c‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,16 +21,15 @@ static void lpt_fdi_reset_mphy(struct intel_display *display)
2121

2222
intel_de_rmw(display, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);
2323

24-
ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
25-
FDI_MPHY_IOSFSB_RESET_STATUS,
26-
FDI_MPHY_IOSFSB_RESET_STATUS, 100, NULL);
24+
ret = intel_de_wait_for_set_us(display, SOUTH_CHICKEN2,
25+
FDI_MPHY_IOSFSB_RESET_STATUS, 100);
2726
if (ret)
2827
drm_err(display->drm, "FDI mPHY reset assert timeout\n");
2928

3029
intel_de_rmw(display, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);
3130

32-
ret = intel_de_wait_us(display, SOUTH_CHICKEN2,
33-
FDI_MPHY_IOSFSB_RESET_STATUS, 0, 100, NULL);
31+
ret = intel_de_wait_for_clear_us(display, SOUTH_CHICKEN2,
32+
FDI_MPHY_IOSFSB_RESET_STATUS, 100);
3433
if (ret)
3534
drm_err(display->drm, "FDI mPHY reset de-assert timeout\n");
3635
}

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