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# AMD XML ISA Specification
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## Motivation
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This documentation gives a detailed description of AMD’s machine-readable instruction set architecture.
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This documentation gives a detailed description of AMD’s machine-readable GPU instruction set architecture specification.
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## Machine-readable ISA specification
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AMD took an effort to develop a fully machine-readable version of their GPU instruction set architecture specification (ISA). This specification is specifically designed to be easily and efficiently read by a computer program. The ISA is specified in XML format and auto generated directly from the hardware description files of AMD GPUs.
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This specification is specifically designed to be easily and efficiently read by a computer program.
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The top-level XML schema is divided into two main elements:
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* Document: contains metadata about the current specification XML file.
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* ISA: describes the Instruction Set Architecture itself for the relevant GPU architecture.
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Here is a top-level view of the schema:
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```
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<Spec>
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<Document>
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<ISA>
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<Architecture>
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<Instructions>
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<Encodings>
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<DataFormats>
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<OperandTypes>
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<FunctionalGroups>
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```
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A detailed description of each of the XML elements in the schema is provided below.
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## AMD GPUs XML ISA Specification
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In this section, we will take a deep dive into the XML specification and break down every single element. The description of elements will be in a breadth first order. Every subsection will describe a single element by stating its parent element and list of child elements.
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### Spec element
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### \<Spec\>
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Hierarchy: **\<Spec\>**
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Description: top level element which holds information about the ISA specification.
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| 1. | Document |[\<Document\>](#document-element)| XML document related information. |
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| 2. | Instruction Set Architecture |[\<ISA\>](#isa-element)| ISA related information. |
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### Document element
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### \<Document\>
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Hierarchy: \<Spec\> → **\<Document\>**
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Description: encapsulates generic information about the XML document.
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| 3. | Release date |\<ReleaseDate\>| The date when the specification was released. |
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| 4. | Schema version |\<SchemaVersion\>| The version of the schema. |
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### ISA element
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### \<ISA\>
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Hierarchy: \<Spec\> → **\<ISA\>**
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Description: contains ISA related information.
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| 5. | Operand types |[\<OperandTypes\>](#operandtypes-element)| Lists all operand types in the architecture. The sub-elements of this element are referenced by an instruction element. It provides information on the types of the operands used by the instruction. Examples of provided information are: is the operand a scalar or a vector register? What is the name of this operand when represented in assembly?|
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| 6. | Functional groups |[\<FunctionalGroups\>](#functionalgroups-element)| Lists all functional groups in the architecture. A function group provides high-level classification of the instructions, such as: vector memory, vector ALU, scalar memory, etc. |
Description: lists all instructions in the architecture. This is the core element of the specification. Every instruction references other XML elements. Examples of provided information by this element: different ways to encode the instruction, the type of operands, the data format of the operand, etc.
| 1. | Instruction encoding (singular) |[\<InstructionEncoding\>](#instructionencoding-element)| One possible encoding version given instruction can be represented in. |
Description: Information about a single operand in the instruction.
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---
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### Encodings element
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### \<Encodings\>
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Hierarchy: \<Spec\> → \<ISA\> → **\<Encodings\>**
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Description: lists all encodings supported by the architecture. Examples of the provided information by this element: instruction sizes, fields of the binary instruction, general description of the encoding.
Description: information about a single encoding in this architecture.
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| -- | -------------- | -------------- | - |
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| 1. | Encoding order | Order | Dictates the order in which encodings should be picked when decoding machine code, with the search halting at the first match of the identifier. |
| 1. | Encoding Identifier (singular) |\<EncodingIdentifier\>| Single unique identifier used to map to the specific encoding. This is the unique identifier of the instruction. The identifier is the combination of the encoding and opcode bits. |
Description: lists all encoding conditions. A condition specifies cases when the encoding can be extended with extra fields such as literal constant, DPP, etc.
Description: a single condition from the list of conditions of the encoding. A condition specifies cases when the encoding can be extended with extra fields such as literal constant, DPP, etc.
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| 1. | Condition name |\<ConditionName\>| Name of the condition. Used as a reference when decoding an instruction and determining which encoding to use.|
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| 2. | Condition expression |\<ConditionExpression\>| An abstract syntax tree. The tree encodes a boolean expression, which if evaluated to true signals that the extended version of the encoding must be used.|
Description: a bitmap holds a detailed breakdown of the fields in the given encoding.
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| -- | ------- | ---------------- | - |
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| 1. | Field |[\<Field\>](#field-element-microcodeformat--bitmap)| A single field from the list of fields in the bitmap. The field specifies the raw binary instruction must be broken down and interpreted.|
Description: lists all data fromats in the architecture. It provides additional information on how the values in the registers should be treated. This element is referenced by the instruction element. Examples of provided information by this element: is the value integer or float? If it is float where is mantissa, exponent and sign?
Description: information about a single data format in this architecture including a data type (descriptor, bits, float), the number of components packed into the given bits, and additional attributes.
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| 4. | Component count |\<ComponentCount\>| Indicates the number of components this format packs into the given bits if data is packed. |
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| 5. | Data attributes |[\<DataAttributes\> → \<BitMap\>](#bitmap-element-dataattributes)| Information about each component in the data format. |
Description: the sub-elements of this element are referenced by an instruction element. It provides information on the types of the operands used by the instruction. Examples of provided information are: is the operand a scalar or a vector register? What is the name of this operand when represented in assembly?
Description: information about a single operand type in the architecture.
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| 2. | Subtypes |\<Subtypes\>| Lists all subtype names that compose the give type. |
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| 3. | Operand predefined values |[\<OperandPredefinedValues\>](#operandpredefinedvalues-element)| Lists all predefined operand values. A predefined value maps encoded integer value in the binary opcode to the corresponding assembly name. |
Description: lists all predefined operand values. A predefined value maps encoded integer value in the binary opcode to the corresponding assembly name.
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| 1. | Operand predefined value |[\<OperandPredefinedValue\>](#operandpredefinedvalue-element)| Maps encoded integer value in the binary opcode to the corresponding assembly name. |
Description: lists all functional groups in the architecture. A function group provides high-level classification of the instructions, such as: vector memory, vector ALU, scalar memory, etc.
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| -- | ---------------- | ---------------- | - |
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| 1. | Functional Group (singular) |[\<FunctionalGroup\>](#functionalgroup-element)| Provides high-level classification of the instruction, such as: vector memory, vector ALU, scalar memory, etc. |
Description: provides the associated subgroup for the instruction in this architecture. For example, a VMEM instruction can have the following subtypes: LOAD, STORE, ATOMIC, TEXTURE, etc.
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